题解 | #脉冲同步电路#

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);
reg data_in_fast;
always @ (posedge clk_fast or negedge rst_n) 
begin
    if(~rst_n) begin
        data_in_fast <= 1'b0;
    end
    else begin
        if(data_in == 1'b1)
            data_in_fast <= ~data_in_fast;
        else 
            data_in_fast <= data_in_fast;
    end 
end 

reg data_in_slow_t1;
reg data_in_slow_t2;
reg data_in_slow_t3;
always @ (posedge clk_slow or negedge rst_n) 
begin
    if(~rst_n) begin
        data_in_slow_t1 <= 1'b0;
        data_in_slow_t2 <= 1'b0;
        data_in_slow_t3 <= 1'b0;
    end
    else begin
        data_in_slow_t1 <= data_in_fast;
        data_in_slow_t2 <= data_in_slow_t1;
        data_in_slow_t3 <= data_in_slow_t2;
    end 
end

assign dataout = data_in_slow_t2 ^ data_in_slow_t3;
endmodule