题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0] out
);
//*************code***********//


reg [1:0]  status;
reg [7:0]  d_tmp;

parameter STATUS_0 = 0;
parameter STATUS_1 = 1;
parameter STATUS_2 = 2;
parameter STATUS_3 = 3;
always@(posedge clk or negedge rst) begin
   if(~rst) begin
       input_grant <= 0;
       out <= 0;
       status <= STATUS_0;
   end
   else begin
      case (status)
        ///0的时候,采用d_tmp=d,是希望理解采集到d的信号
        2'd0: begin  status <= STATUS_1;d_tmp = d; out <= d_tmp ; input_grant <= 1;end
        2'd1: begin  status <= STATUS_2;d_tmp <= d_tmp; out <= d_tmp * 3;input_grant <= 0;end
        2'd2: begin  status <= STATUS_3;d_tmp <= d_tmp; out <= d_tmp * 7;input_grant <= 0;end
        2'd3: begin  status <= STATUS_0;d_tmp <= d; out <= d_tmp * 8;input_grant <= 0;end
      endcase
   end
end
//*************code***********//
endmodule