题解 | #根据RTL图编写Verilog程序#

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
	);
	reg q1;
	always@(posedge clk,negedge rst_n)
		begin
			if(!rst_n)
				q1<=0;
			else
				q1<=data_in;
		end
	always@(posedge clk,negedge rst_n)
		begin
			if(!rst_n)
				data_out<=0;
			else
				data_out<=!q1&data_in;
		end	

endmodule