题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//

parameter N=7;
reg [2:0] cnt;
reg div7, div7n;

always @(posedge clk_in or negedge rst) begin
    if(~rst) 
       cnt <= 0;
    else
       cnt <= cnt==N-1 ? 0 : cnt+1;
end

always @(posedge clk_in or negedge rst) begin
    if(~rst) 
       div7 <= 0;
    else if(cnt==N-1 | cnt==N-1>>1)
       div7 <= ~div7;
    else
       div7 <= div7;
end

always @(negedge clk_in or negedge rst) begin
    if(~rst) 
       div7n <= 0;
    else if(cnt==N-1 | cnt==N-1>>1)
       div7n <= ~div7n;
    else
       div7n <= div7n;
end

assign clk_out7 = div7|div7n;

//*************code***********//
endmodule

//*************测试用testbench***********//
`timescale 1ns/1ns

module testbench();
	reg clk=0;
	always #1 clk = ~clk;  // Create clock with period=10
// A testbench
    
reg rst;
wire clk7;
odo_div_or inst1(rst, clk, clk7);

initial begin
  rst=0;
  #2 rst=1;
  #100 $finish;
end
    
    
    
//end    
  initial begin
    $dumpfile("out.vcd");
    // This will dump all signal, which may not be useful
    //$dumpvars;
    // dumping only this module
    //$dumpvars(1, testbench);
    // dumping only these variable
    // the first number (level) is actually useless
    $dumpvars(0, testbench);
end  
    
endmodule