题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg		[8:0]	r_sft;

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		r_sft <= 9'h1FF;
	else
		r_sft <= {r_sft[8:0],a};

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		match <= 1'b0;
	else
		match <= ~r_sft[8] & r_sft[7] & r_sft[6]
				& r_sft[2] & r_sft[1] & ~r_sft[0];


endmodule