题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output 	wire	[7:0]	d
);

wire	[7:0]	x;
reg		[7:0]	y;

always @(posedge clk)
	y <= c;		//y打一拍

sub_mod m1
(
	.clk	(clk	),
	.rst_n	(rst_n	),
	.a		(a		),
	.b		(b		),
	
	.c		(x		)
);

sub_mod m2
(
	.clk	(clk	),
	.rst_n	(rst_n	),
	.a		(x		),
	.b		(y		),
	
	.c		(d		)
);


endmodule

module sub_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	
	output 	reg		[7:0]c
);

wire	[7:0]	c_net;

assign	c_net = (a < b) ? a : b;

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		c <= 8'b0;
	else
		c <= c_net;

endmodule