题解 | #根据状态转移表实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
      input                A   ,
      input                clk ,
      input                rst_n,
 
      output   wire        Y   
);

reg [1:0] qq;
reg y;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        qq <= 0;
        y <= 0;
    end
    else begin
        if (!A) begin
            qq = qq + 1;
            case (qq)
                0:  begin   y <= 0;     end
                1:  begin   y <= 0;     end
                2:  begin   y <= 0;     end
                3:  begin   y <= 1;     end
            endcase
        end
        else begin
            qq = qq - 1;
            case (qq)
                0:  begin   y <= 0;     end
                1:  begin   y <= 0;     end
                2:  begin   y <= 0;     end
                3:  begin   y <= 1;     end
            endcase
        end
    end
end
assign Y = y;
endmodule