题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,
// 注意添加reg，题目中说明了输出是reg类型
output reg [4:0]out,
output reg validout
);
//*************code***********//
reg [15:0] din;
always @(posedge clk or negedge rst) begin
    if (!rst) begin
        din <= 0;
        out <= 0;
        validout <= 0;    
    end
    else begin
        case(sel)
            0:  begin
                din <= d; // 保存此时的输入
                out <= 0; // sel为0时，输出重置为0
                validout <= 0;
            end
            1:  begin
                out <= din[3:0] + din[7:4];
                validout <= 1;
            end
            2:  begin
                out <= din[3:0] + din[11:8];
                validout <= 1;
            end
            3:  begin
                out <= din[3:0] + din[15:12];
                validout <= 1;
            end
        endcase
    end
end
//*************code***********//
endmodule