题解 | #任意小数分频#

`timescale 1ns/1ns

module div_M_N(
 input  wire clk_in,
 input  wire rst,
 output wire clk_out
);
parameter M_N = 8'd87; 
parameter c89 = 8'd24; // 8/9时钟切换点
parameter div_e = 5'd8; //偶数周期
parameter div_o = 5'd9; //奇数周期
//*************code***********//

reg [$clog2(M_N) - 1 : 0] cnt;
reg flag;

always@(posedge clk_in or negedge rst) begin
    if(~rst) begin
        cnt <= '0;     
    end
    else 
        cnt <=  cnt == M_N - 1 ? 0 : cnt + 1;
end

reg clk_out_r;
always@(posedge clk_in or negedge rst) begin
    if(~rst) begin
        clk_out_r <= '0;     
    end
    else 
        clk_out_r <= cnt < c89 ? ((cnt % div_e) < (div_e >> 1)) : (((cnt - c89) % div_o) < (div_o >> 1));
end

assign clk_out = clk_out_r;
//*************code***********//
endmodule