题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

reg [2:0] cnt;
reg clock1, clock2;

//*************code***********//

always@(posedge clk_in or negedge rst) begin
	if(!rst) begin
		cnt <= '0;
	end
    else
        cnt <= cnt >= 6 ? 0 : cnt + 1;

end

always@(posedge clk_in or negedge rst) begin
	if(!rst) begin
		clock1 <= '0;
	end
    else
        clock1 <= ((cnt == 3) || (cnt == 6)) ? !clock1 : clock1;

end
always@(negedge clk_in or negedge rst) begin
	if(!rst) begin
		clock2 <= '0;
	end
    else
        clock2 <= ((cnt == 3) || (cnt == 6)) ? !clock2 : clock2;
end
//*************code***********//
assign clk_out7 = clock1 || clock2;
endmodule