题解 | #时钟分频（偶数）#

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
reg [2:0] cnt;

always@(posedge clk_in or negedge rst) begin
	if(!rst) 
		cnt <= '1;
    else
        cnt <= cnt + 1;
end

assign {clk_out8, clk_out4, clk_out2}  = ~cnt;

//*************code***********//
endmodule