题解 | #加减计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input mode,
	output reg [3:0]number,
	output reg zero
	);

    reg [3:0]cnt;
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
		    cnt <= 0;
		else 
		cnt <= mode ? (cnt == 9 ? 0 : cnt+1) : (cnt == 0 ? 9 : cnt-1);
	end

	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
		    zero <= 0;
		else zero <= cnt==0;
	end
    
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
		    number <= 0;
		else number <= cnt;
	end

endmodule