题解 | #根据状态转移表实现时序电路#
根据状态转移表实现时序电路
https://www.nowcoder.com/practice/455c911bee0741bf8544a75d958425f7
`timescale 1ns/1ns module seq_circuit( input A , input clk , input rst_n, output wire Y ); reg D0,D1; always@(posedge clk or negedge rst_n) begin if(!rst_n)begin D1 = 0; D0 = 0; end else begin D1 = A ^ D1 ^ D0; D0 = ~D0; end end assign Y = D1 & D0; endmodule