题解 | #自动贩售机1#

`timescale 1ns/1ns
module seller1(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire d3 ,
	
	output reg out1,
	output reg [1:0]out2
);
//*************code***********//
parameter idle=0,s0=1,s1=2,s2=3,s3=4,s4=5,s5=6;
reg [2:0] cs,ns;
always@(posedge clk or negedge rst)begin
	if(!rst)cs<=idle;
	else cs<=ns;
end
always@(*)begin
	if(!rst)ns=idle;
	else begin
		case(cs)
		idle:ns=d1?s0:d2?s1:d3?s3:ns;//因为组合逻辑电路在任意时刻改变激励值都会使改变输出值，所以需要用ns=ns来锁存值
		s0:ns=d1?s1:d2?s2:d3?s4:ns;
		s1:ns=d1?s2:d2?s3:d3?s5:ns;
		s2:ns=idle;
		s3:ns=idle;
		s4:ns=idle;
		s5:ns=idle;
		default:ns=idle;
		endcase

	end
end
always@(posedge clk or negedge rst)begin
	if(!rst)begin
		out1<=0;
		out2<=0;
	end
	else begin
		case(ns)
		idle:begin
			out1<=0;
			out2<=0;
		end
		s0:begin
			out1<=0;
			out2<=0;
		end
		s1:begin
			out1<=0;
			out2<=0;
		end
		s2:begin
			out1<=1;
			out2<=0;
		end
		s3:begin
			out1<=1;
			out2<=1;
		end
		s4:begin
			out1<=1;
			out2<=2;
		end
		s5:begin
			out1<=1;
			out2<=3;
		end
		default:begin
			out1<=0;
			out2<=0;
		end
		endcase
	end
end

//*************code***********//
endmodule