题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
	parameter [3:0]
	IDLE = 4'd0, S1 = 4'd1,
	S2 = 4'd2, S3 = 4'd3,
	S4 = 4'd4, S5 = 4'd5,
	S6 = 4'd6, S7 = 4'd7, S8 = 4'd8;
	reg [3:0] NS, CS;

	always @(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
		CS <= IDLE;
		else
		CS <= NS;
	end

	always @(*)
	begin
		NS = IDLE;
		case(CS)
		IDLE: NS = a? IDLE : S1;
		S1: NS = a? S2 : S1;
		S2: NS = a? S3 : S1;
		S3: NS = a? S4 : S1;
		S4: NS = a? IDLE : S5;
		S5: NS = a? S2 : S6;
		S6: NS = a? S2 : S7;
		S7: NS = a? S8 : S1;
		S8: NS = a? S3 : S1;
		default: NS = IDLE;
		endcase
	end


	always @(posedge clk or negedge rst_n)
	begin
		if(!rst_n)
		match <= 1'b0;
		else begin
			if(CS == S8)
			match <= 1'b1;
			else
			match <= 1'b0;
		end
	end

	/*reg [7:0] a_temp;
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
		a_temp <= 8'b1111_1111;
		else
		begin
			a_temp <= {a_temp[6:0], a};
		end
	end

	always @(posedge clk or negedge rst_n)begin
		if(!rst_n)
		match <= 1'b0;
		else begin
			if(a_temp == 8'b0111_0001)
			match <= 1'b1;
			else 
			match <= 1'b0;
		end
	end*/
  
endmodule