题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg 			[8:0]				line;




always@(posedge clk or negedge rst_n)
	if(!rst_n) begin
		line 	<= 9'd0;
	end
	else begin
		line <= {a,line[8:1]};
	end



always@(posedge clk or negedge rst_n)begin
	if(!rst_n) begin
		match <= 1'b0;
	end
	else if((line_a==3'b110)&&(line_c==3'b011))
		match <= 1'b1;
	else
		match <= 1'b0;
end

// reg				[2:0] 				line_a,line_c;
// always@(posedge clk or negedge rst_n)
// 	if(!rst_n) begin
// 		line_a 	<= 3'b000;
// 		line_c	<= 3'b000;
// 	end
// 	else begin
// 		line_a <= line[2:0];
// 		line_c <= line[8:6];
// 	end

wire				[2:0] 				line_a,line_c;
assign line_a = line[2:0];
assign line_c = line[8:6];




  
endmodule