题解 | #信号顺序调整#

`timescale 1ns/1ns

module top_module(
    input  [15:0]in,
    output [15:0]out
);
   wire [3:0] a, b, c, d;
   assign {a[3:0], b[3:0], c[3:0], d[3:0]} = in;
   assign out = {d, c, b, a};
endmodule