题解 | #同步FIFO#

`timescale 1ns/1ns

/**********************************RAM************************************/
module dual_port_RAM #(parameter DEPTH = 16,
					   parameter WIDTH = 8)(
	 input wclk
	,input wenc
	,input [$clog2(DEPTH)-1:0] waddr  
	,input [WIDTH-1:0] wdata      	
	,input rclk
	,input renc
	,input [$clog2(DEPTH)-1:0] raddr  
	,output reg [WIDTH-1:0] rdata 		
);

reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];

always @(posedge wclk) begin
	if(wenc)
		RAM_MEM[waddr] <= wdata;
end 

always @(posedge rclk) begin
	if(renc)
		rdata <= RAM_MEM[raddr];
end 

endmodule  

/**********************************SFIFO************************************/
module sfifo#(
	parameter	WIDTH = 8,
	parameter 	DEPTH = 16
)(
	input 					clk		, 
	input 					rst_n	,
	input 					winc	,
	input 			 		rinc	,
	input 		[WIDTH-1:0]	wdata	,

	output reg				wfull	,
	output reg				rempty	,
	output wire [WIDTH-1:0]	rdata
);

wire	wenc,renc	;
reg	[$clog2(DEPTH):0]	waddr,raddr	;

assign	wenc = winc & !wfull;
assign	renc = rinc & !rempty;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        waddr   <=  0;
    else    if(wenc)
        waddr   <=  waddr + 1;
    else
        waddr   <=  waddr;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        raddr   <=  0;
    else    if(renc)
        raddr   <=  raddr + 1;
    else
        raddr   <=  raddr;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        wfull   <=  1'b0;
    else    if (waddr == {!raddr[$clog2(DEPTH)],raddr[$clog2(DEPTH)-1:0]})
        wfull   <=  1'b1;
    else
        wfull   <=  1'b0;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        rempty  <=  1'b0;
    else    if(raddr == waddr )
        rempty  <=  1'b1;
    else
        rempty  <=  1'b0;

dual_port_RAM 
#(
    .DEPTH(16),
    .WIDTH(8 )
)
u0
(
	. wclk(clk),
	. wenc(wenc),
	. waddr(waddr[$clog2(DEPTH)-1:0]),  
	. wdata(wdata),     	
	. rclk(clk),
	. renc(renc),
	. raddr(raddr[$clog2(DEPTH)-1:0]), 
	. rdata(rdata) 		
);

endmodule