题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

reg[5:0]data_reg;//缓存拼接数据的寄存器
reg[2:0]data_cnt;//计数器的寄存器

//ready信号
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		ready_a<=1'b0;
	else
		ready_a<=1'b1;
end

//计数器计数过程和计数范围
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		data_cnt <= 3'b0;
	else if(valid_a&&ready_a)
		data_cnt <= (data_cnt == 3'd5)?3'b0:(data_cnt + 1'b1);
end

//数据缓存寄存器
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		data_reg <= 3'b0;
	else if(valid_a&&ready_a)
		data_reg <= {data_a,data_reg[5:1]};
end

//valid_b和data_b
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		valid_b <= 1'b0;
		data_b <= 6'b0;
	end
	else if(data_cnt == 3'd5)begin //这句话控制了data_b和valid_b是已接收到6个数据后才升高
		valid_b <= 1'b1;
		data_b <= {data_a,data_reg[5:1]};
	end
	else
		valid_b <= 1'b0;
end

endmodule

很有启发的一道题