题解 | #自动贩售机1#

`timescale 1ns/1ns
module seller1(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire d3 ,
	
	output reg out1,
	output reg [1:0]out2
);
//*************code***********//
parameter S0 = 3'd0;
parameter S0_5 = 3'd1;
parameter S1 = 3'd2;
parameter S1_5 = 3'd3;
parameter S2 = 3'd4;
parameter S2_5 = 3'd5;
parameter S3 = 3'd6;

reg [2:0] c_state;
reg [2:0] n_state;
always @(posedge clk or negedge rst) begin
	if(!rst) begin
		c_state <= S0;
	end
	else begin
		c_state <= n_state;
	end
end

always @(*) begin
	if(!rst) begin
		n_state <= S0;
	end
	else begin
		case(c_state)
			S0:
//				case({d1,d2,d3})
//                    3'b100: n_state <= S0_5;
//                    3'b010: n_state <= S1;
//                    3'b001: n_state <= S2;
//                    default: n_state <= n_state;
//				endcase
				n_state <= 	({d1,d2,d3} == 3'b100) ? S0_5:
							({d1,d2,d3} == 3'b010) ? S1:
							({d1,d2,d3} == 3'b001) ? S2:n_state;
			S0_5:
//			    case({d1,d2,d3})
//                    3'b100: n_state <= S1;
//                    3'b010: n_state <= S1_5;
//                    3'b001: n_state <= S2_5;
//                    default: n_state <= n_state;
//				endcase
				n_state <= 	({d1,d2,d3} == 3'b100) ? S1:
							({d1,d2,d3} == 3'b010) ? S1_5:
							({d1,d2,d3} == 3'b001) ? S2_5:n_state;
			S1:
//				case({d1,d2,d3})
//                    3'b100: n_state <= S1_5;
//                    3'b010: n_state <= S2;
//                    3'b001: n_state <= S3;
//                    default: n_state <= n_state;
//				endcase
				n_state <= 	({d1,d2,d3} == 3'b100) ? S1_5:
							({d1,d2,d3} == 3'b010) ? S2:
							({d1,d2,d3} == 3'b001) ? S3:n_state;
			default: n_state <= S0;
		endcase
	end
end

always @(*) begin
	if(!rst) begin
		out1 <= 0;
	end
	else begin
		out1 <= ((c_state == S1_5 | c_state == S2 | c_state == S2_5 | c_state == S3));
	end
end

always @(*) begin
	if(!rst) begin
		out2 <= 0;
	end
	else begin
		out2 <= (c_state == S1_5)? 0:
				(c_state == S2)? 1:
				(c_state == S2_5)? 2:
				(c_state == S3)? 3:0;
	end
end

//*************code***********//
endmodule