题解 | #奇偶校验#
奇偶校验
https://www.nowcoder.com/practice/67d4dd382bb44c559a1d0a023857a7a6
`timescale 1ns/1ns module odd_sel( input [31:0] bus, input sel, output check ); //*************code***********// reg check; always @(*) begin if(sel) check<=^bus; else check<=!(^bus); end //*************code***********// endmodule