题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

reg [3:0]    seq    ;
always@(posedge clk or negedge rst_n)    begin
	if(!rst_n)    begin
		seq <= 0 ;
	end
	else if(data_valid) begin
    	seq <= {seq[2:0],data};   //重点是这个
	end
end

always@(posedge clk or negedge rst_n)    begin
	if(!rst_n)    begin
		match <= 0 ;
	end
	else if({seq[2:0],data} == 'b0110)
		match <= 1;
	else 
		match <= 0 ;
end

endmodule