题解 | #根据状态转移图实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);
reg [1:0] state = 2'b00;

always@(posedge clk or negedge rst_n)
begin
    if(~rst_n)
    begin
        state <= 2'b00;
    end
    else
    begin
        case(state)
        2'b00: state <= C? 2'b01:2'b00;
        2'b01: state <= C? 2'b01:2'b11;
        2'b10: state <= C? 2'b10:2'b00;
        2'b11: state <= C? 2'b10:2'b11;
        endcase
    end
end
assign Y = state[1]&state[0] | state[1]&(~state[0])&C;

endmodule