题解 | #4bit超前进位加法器电路#

`timescale 1ns/1ns

module lca_4(
	input		[3:0]       A_in  ,
	input	    [3:0]		B_in  ,
    input                   C_1   ,
 
 	output	 wire			CO    ,
	output   wire [3:0]	    S
);

task ADD;
input A,B,CIN;
output [1:0]C;
reg S,COUT;
begin
	S = A^B^CIN;
	COUT = (A&B)|(A&CIN)|(B&CIN);
	C = {COUT,S};
end
endtask
reg [1:0]S0,S1,S2,S3;
always@(A_in or B_in or C_1)
begin
	ADD(A_in[0],B_in[0],C_1,S0);
	ADD(A_in[1],B_in[1],S0[1],S1);
	ADD(A_in[2],B_in[2],S1[1],S2);
	ADD(A_in[3],B_in[3],S2[1],S3);
end
assign S = {S3[0],S2[0],S1[0],S0[0]};
assign CO = S3[1];
    
endmodule