题解 | #加减计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input mode,

	output reg [3:0]number,
	output reg zero
);

reg [3:0]num_reg;

always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    num_reg <= 4'b0;
	else if (mode == 1'b1)
	    begin
			if (num_reg == 4'd9)
			    num_reg <= 4'b0;
			else 
			    num_reg <= num_reg + 1'b1;
		end
	else if (mode == 1'b0)
	    begin
			if (num_reg == 4'd0)
			    num_reg <= 4'd9;
			else 
			    num_reg <= num_reg - 1'b1;
		end
	else 
	    num_reg <= num_reg;

always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    number <= 4'b0;
	else
	    number <= num_reg;

always@(posedge clk or negedge rst_n)
    if(rst_n == 1'b0)
	    zero <= 1'b0;
	else if (num_reg == 4'd0 && mode == 1'b1)
	    zero <= 1'b1;
	else if (num_reg == 4'd0 && mode == 1'b0)
	    zero <= 1'b1;
	else
	    zero <= 1'b0;

endmodule