题解 | #根据状态转移表实现时序电路#(三段式状态机实现)

`timescale 1ns/1ns

module seq_circuit(
      input                A   ,
      input                clk ,
      input                rst_n,
 
      output   wire        Y   
);


reg [3:0]  cur_state;
reg [3:0]  nex_state;


////////////////三段式状态机////////////////////

//第一段 描述状态转移关系
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        cur_state <= 2'b00     ;
    else 
        cur_state <= nex_state ;
end

//第二段 组合逻辑描述状态转移逻辑

always@(*)begin
    case(cur_state)
        2'b00: nex_state = (A == 0)? 2'b01:2'b11;
        2'b01: nex_state = (A == 0)? 2'b10:2'b00;
        2'b10: nex_state = (A == 0)? 2'b11:2'b01;
        2'b11: nex_state = (A == 0)? 2'b00:2'b10;
        default: nex_state = 2'b00;
    endcase
end

//第三段 描述输出
assign Y =  ((cur_state == 2'b11 & A == 0)| (cur_state == 2'b11 & A == 1))?1'b1:1'b0;
endmodule