题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

	reg [8:0] data;
	always @(posedge clk or negedge rst_n) begin
		if (!rst_n) begin
			data <= 0;
		end
		else begin
			data <= {a,data[8:1]};
		end
	end

	always @(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			match <= 0;
		end
		else if ((data[8:6]== 3'b011) & (data[2:0] == 3'b110)) begin
			match <= 1;
		end
		else begin
			match <= 0;
		end
	end


  
endmodule