题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n	,
	input				   valid_in	,
    input	    [7:0]	   data_in	,
 
 	output	reg			   valid_out,
    output  reg [15:0]	   data_out
);
    reg [7:0] data_lock;
    reg [1:0]      cnt;
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            cnt <= 2'b0;
        else if(cnt==2'b1 && valid_in)
            cnt <= 2'b0 ;
        else if(valid_in)
            cnt <= cnt+2'b1;
    end
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            data_lock <= 8'b0 ;
        else 
            data_lock <= data_in ;
    end
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            data_out <= 16'b0;
        else if(cnt==2'b1 &&valid_in)
            data_out <= {data_lock,data_in};
    end
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            valid_out <= 1'b0;
        else if(cnt==2'b1 &&valid_in)
            valid_out <= 1'b1;
        else 
            valid_out <= 1'b0;

    end
endmodule