题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
reg apre;
always @(posedge clk or negedge rst_n)
	begin
		if(~rst_n)
			begin
				rise <= 0;
				down <= 0;
				apre <= 0;
			end
		else
			begin
				apre <= a;
				if(~apre & a)
					rise <= 1'b1;
				else
					rise <= 1'b0;
				if(apre & ~a)
					down <= 1'b1;
				else
					down <= 1'b0;
			end
	end	
endmodule