题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
reg [2:0] cnt;
reg   out;
always @(clk_in or negedge rst)
begin
if(!rst)
begin
cnt<=3'd1;
end
else
begin
cnt<= (cnt== 3'd7) ? 3'd1 : cnt+3'd1;
end
end

always @(clk_in or negedge rst)
begin
if(!rst)
begin
out=1'b0;
end
else
begin
out= cnt==7 ? ~out : out;
end
end


assign clk_out7=out;
//*************code***********//
endmodule