题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output reg validout
);
//*************code***********//
reg [15:0]data_lock;
//寄存器data——lock放的时候要注意
always @(posedge clk or negedge rst)
begin
    if(!rst)
    data_lock<=0;
    else if(!sel)
    data_lock<=d;
end
always@(posedge clk or negedge rst)
begin
    if(!rst)
    begin
out <= 'b0;
        validout <=0;
    end
    else
    begin
        
        case(sel)
        0:begin
            out<='b0;
            validout <=0;
        end
        1:begin
            out<=data_lock[3:0]+data_lock[7:4];
            validout <=1;
        end
        2:begin
            out<=data_lock[3:0]+data_lock[11:8];
            validout <=1;
        end
        3:begin
            out<=data_lock[3:0]+data_lock[15:12];
            validout <=1;
        end
        endcase
    end
end
//*************code***********//
endmodule