题解 | #根据状态转移图实现时序电路#
根据状态转移图实现时序电路
https://www.nowcoder.com/practice/e405fe8975e844c3ab843d72f168f9f4
`timescale 1ns/1ns module seq_circuit( input C , input clk , input rst_n, output wire Y ); reg out,d0,d1; always @(posedge clk or negedge rst_n) begin if(!rst_n) begin out<=1'b0; d1<=1'b0; d0<=1'b0; end else begin d0<=d0&~C|~d1&C; d1<=d0&~C|d1&C; end end assign Y=d0&d1|d1&C; endmodule
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