题解 | #ROM的简单实现#

`timescale 1ns/1ns
module rom(
	input clk,
	input rst_n,
	input [7:0]addr,
	
	output [3:0]data
);
reg [3:0] d7,d6,d5,d4,d3,d2,d1,d0;
always @(posedge clk or negedge rst_n) begin
	if (~rst_n) begin
		d0 <= 0;
		d1 <= 2;
		d2 <= 4;
		d3 <= 6;
		d4 <= 8;
		d5 <= 10;
		d6 <= 12;
		d7 <= 14; 
	end
end
assign data = (addr==7)?d7:
			((addr==6)?d6:
			((addr==5)?d5:
			((addr==4)?d4:
			((addr==3)?d3:
			((addr==2)?d2:
			((addr==1)?d1:
			((addr==0)?d0:0)))))));
endmodule

前面初始化用寄存器，后面使用选择来输出。