题解 | #移位运算与乘法#

`timescale 1ns/1ns

module multi_sel(
  input [7:0]d ,
  input clk,
  input rst,
  output input_grant,
  output [10:0]out
  );
  //*************code***********//
  reg [10:0]out_reg = 11'd0;
  reg input_grant_reg = 1'd0;
  reg [7:0] din = 8'd0;
  reg [3:0]status = 4'd0;

  parameter Status_be = 4'd1; 
  parameter Status_x1 = 4'd2; 
  parameter Status_x3 = 4'd3; 
  parameter Status_x7 = 4'd4; 
  parameter Status_x8 = 4'd5; 
  parameter Status_end = 4'd6; 
  parameter Status_wait = 4'd7; 
  
  assign  out = out_reg;
  assign  input_grant = input_grant_reg;

  always @(posedge clk)
  begin
      if(rst==1'd0)
      begin
          status <= 4'd0;
          input_grant_reg <= 1'd0;
          out_reg <= 11'd0;
      end
  end
  
  always @(posedge rst)
  begin
      status <= Status_x1;
  end
 
  always @(posedge clk)
  begin
      case(status)  
      Status_x1: begin
          din <= d;
          out_reg <= d;
          input_grant_reg <= 1'd1;
          status <= Status_x3;
      end
      Status_x3: begin
          out_reg <= (din<<2) - din ;
          input_grant_reg <= 1'd0;
          status <= Status_x7;
      end    
      Status_x7: begin
          out_reg <= (din<<3) - din ;
          status <= Status_x8;
      end   
      Status_x8: begin
          out_reg <= din<<3;
          status <= Status_x1;
      end
      default:
      begin
        status <= Status_x1;        
      end
      endcase
  end
  
  //*************code***********//
  endmodule