题解 | #状态机-非重叠的序列检测#

注意：判断输出flag需要用nstata来判断。

always@(posedge clk or negedge rst)
		if(~rst)
			flag <= 0;
		else
			flag <= nstata==S_10111? 1:0;

`timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
	parameter IDLE=0, S_1=1, S_10=2, S_101=3, S_1011=4, S_10111=5;
	reg [4:0] stata, nstata;

	always@(posedge clk or negedge rst)
		if(~rst)
			stata <= IDLE;
		else
			stata <= nstata;

	always@(*)begin
		case(stata)
			IDLE: nstata <= data==1? S_1: IDLE;
			S_1: nstata <= data==1? S_1: S_10;
			S_10: nstata <= data==1? S_101: IDLE;
			S_101: nstata <= data==1? S_1011: S_10;
			S_1011: nstata <= data==1? S_10111: S_10;
			S_10111: nstata <= data==1? S_1: IDLE;
			default: nstata <= IDLE;
		endcase
	end
	always@(posedge clk or negedge rst)
		if(~rst)
			flag <= 0;
		else
			flag <= nstata==S_10111? 1:0;

//*************code***********//
endmodule