题解 | #单端口RAM#

`timescale 1ns/1ns

module RAM_1port(
    input clk,
    input rst,
    input enb,
    input [6:0]addr,
    input [3:0]w_data,
    output wire [3:0]r_data
);
//*************code***********//
reg [3:0] ram [0:127];
integer i;

always@(posedge clk,negedge rst)
    begin
        if(rst==1'b0) begin
            for(i=0;i<=127;i=i+1)
                ram[i] <= 0;
        end
        else if(enb == 1'b1) ram[addr] <= w_data;
    end

    assign r_data = enb?0:ram[addr];
//*************code***********//
endmodule