题解 | #序列检测器（Moore型）#

`timescale 1ns/1ns

module det_moore(
   input                clk   ,
   input                rst_n ,
   input                din   ,
 
   output	reg         Y   
);

reg [2:0] cstate, nstate;

always@(posedge clk, negedge rst_n) begin
    if(rst_n == 1'b0) cstate <= 3'b000;
    else cstate <= nstate;
end

always@(*) begin
    if(rst_n == 1'b0) nstate <= 3'b000;
    case(cstate)
    3'b000: begin
        if(din==1'b1) nstate <= 3'b001;
        else nstate <= 3'b000;
    end
    3'b001:begin
        if(din==1'b1) nstate <= 3'b010;
        else nstate <= 3'b000;
    end
    3'b010:begin
        if(din==1'b1) nstate <= 3'b010;
        else nstate <= 3'b011;
    end
    3'b011:begin
        if(din==1'b1) nstate <= 3'b100;
        else nstate <= 3'b000;
    end
    default: nstate <= 3'b000;
    endcase 
end

always@(posedge clk, negedge rst_n) begin
    if(rst_n == 1'b0) Y <= 0;
    else if(cstate == 3'b100) Y <= 1;
    else  Y <= 0;
end

endmodule