题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
//定义分频系数
parameter CLK_INV = 3'd7;
parameter CLK_INV1 = CLK_INV/2;

//时钟两触发沿对应信号
reg clk_out7_n;
reg clk_out7_p;

//分频计数器
reg [2:0]cnt;

//分频计数器计数
always@(posedge clk_in or negedge rst)begin
    if(!rst)
        cnt <= 3'd0;
    else if(cnt == CLK_INV-1)
        cnt <= 3'd0;
    else    
        cnt <= cnt + 1'b1;
end

//上升沿触发
always@(posedge clk_in or negedge rst)begin
    if(!rst)
        clk_out7_p <= 1'b0;
    else if(cnt == CLK_INV1)
        clk_out7_p <= 1'b1;
    else if(cnt == CLK_INV-1)
        clk_out7_p <= 1'b0;
    else    
        clk_out7_p <= clk_out7_p;
end

//下降沿触发
always@(negedge clk_in or negedge rst)begin
    if(!rst)
        clk_out7_n <= 1'b0;
    else if(cnt == CLK_INV1)
        clk_out7_n <= 1'b1;
    else if(cnt == CLK_INV-1)
        clk_out7_n <= 1'b0;
    else    
        clk_out7_n <= clk_out7_n;
end

//奇数倍分频
assign clk_out7 = clk_out7_p | clk_out7_n;
//*************code***********//
endmodule