题解 | #数据串转并电路#

容易出错的地方：!valid_a 的时候，计数i 不是归0 而是保持原来的技术

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

	reg [5:0] temp;
	integer i=0;



always @(posedge clk or negedge rst_n)
begin
	if(!rst_n) 
		ready_a <= 0;
	else 
		ready_a <= 1;

end

always @(posedge clk or negedge rst_n)
begin
	if(!rst_n) 
		i <= 0;
	else if (!valid_a)
		i <= i;
	else
	begin
		i <= i<6? i+1:1;
		temp <= {data_a,temp[5:1]};
	end
end

always @(*)(1444584)
begin
	if (!rst_n || !ready_a) 
	begin
		valid_b = 0;
		data_b = 0;
	end
	else if (i ==6)
	begin
		valid_b = 1;
		data_b = temp;
	end
	else
		valid_b = 0;
end

endmodule