题解 | #任意奇数倍时钟分频#

`timescale 1ns/1ns

module clk_divider
    #(parameter dividor = 5)
( 	input clk_in,
	input rst_n,
	output clk_out
);

	reg [3:0] cnt;
	reg clk_out1,clk_out2;

	always @(posedge clk_in or negedge rst_n) begin
		if(rst_n == 1'b0)
			cnt <= 4'd0;
		else if(cnt == dividor - 1)
			cnt <= 'd0;
		else
			cnt <= cnt + 1'b1;
	end

	always @(posedge clk_in or negedge rst_n) begin
		if(rst_n == 1'b0)
			clk_out1 <= 1'b0;
		else if(cnt == (dividor-1)>>1)
			clk_out1 <= 1'b1;
		else if(cnt == dividor-1)
			clk_out1 <= 1'b0;
		else
			clk_out1 <= clk_out1;
	end

	always @(negedge clk_in or negedge rst_n) begin
		if(rst_n == 1'b0)
			clk_out2 <= 1'b0;
		else if(cnt == (dividor-1)>>1)
			clk_out2 <= 1'b1;
		else if(cnt == dividor-1)
			clk_out2 <= 1'b0;
		else
			clk_out2 <= clk_out2;
	end

	assign clk_out = clk_out1 | clk_out2;
    
endmodule