题解2 | #根据状态转移表实现时序电路#

根据状态机写

`timescale 1ns/1ns

module seq_circuit(
      input                A   ,
      input                clk ,
      input                rst_n,
 
      output   wire        Y   
);

//用状态机写

reg [1:0] curr_state;
reg [1:0] nxt_state;

always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)
    curr_state <= 2'b0;
    else
    curr_state <= nxt_state;
end

always @(*)(1444584)
begin
    case(curr_state)
    2'b00: nxt_state = A? 2'b11:2'b01;
    2'b01: nxt_state = A? 2'b00:2'b10;
    2'b10: nxt_state = A? 2'b01:2'b11;
    2'b11: nxt_state = A? 2'b10:2'b00;
    default: nxt_state = 2'b00;
    endcase
end

assign Y = curr_state[1] & curr_state[0];

endmodule