题解 | #同步FIFO#

`timescale 1ns/1ns

/**********************************RAM************************************/
module dual_port_RAM #(parameter DEPTH = 16,
					   parameter WIDTH = 8)(
	 input wclk
	,input wenc
	,input [$clog2(DEPTH)-1:0] waddr  
	,input [WIDTH-1:0] wdata      	
	,input rclk
	,input renc
	,input [$clog2(DEPTH)-1:0] raddr  
	,output reg [WIDTH-1:0] rdata 		
);

reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];

always @(posedge wclk) begin
	if(wenc)
		RAM_MEM[waddr] <= wdata;
end 

always @(posedge rclk) begin
	if(renc)
		rdata <= RAM_MEM[raddr];
end 

endmodule  

/**********************************SFIFO************************************/
module sfifo#(
	parameter	WIDTH = 8,
	parameter 	DEPTH = 16
)(
	input 					clk		, 
	input 					rst_n	,
	input 					winc	,
	input 			 		rinc	,
	input 		[WIDTH-1:0]	wdata	,

	output reg				wfull	,
	output reg				rempty	,
	output wire [WIDTH-1:0]	rdata
);
reg [$clog2(DEPTH):0]waddr;
reg	[$clog2(DEPTH):0]raddr;
//waddr
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		waddr<=0;
	else if(!wfull&&winc)
		waddr<=waddr+1'd1;
	else
	    waddr<=waddr;
end
//raddr
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		raddr<=0;
	else if(!rempty&rinc)
		raddr<=raddr+1'd1;
	else
	    raddr<=raddr;
end
//wfull
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		wfull<=0;
	else if(waddr=={!raddr[4],raddr[3:0]})
		wfull<=1'd1;
	else
	    wfull<=0;
end
//rempty
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		rempty<=0;
	else if(raddr==waddr)
		rempty<=1'd1;
	else
	    rempty<=0;
end
wire wen;
wire ren;
assign wen=!wfull & winc;
assign ren=!rempty & rinc;
dual_port_RAM  #(.DEPTH(DEPTH) ,
				 .WIDTH(WIDTH))
u1
	(
		.wclk(clk),
		.wenc(wen),
		.waddr(waddr[3:0]),
		.wdata (wdata),    	
		.rclk(clk),
		.renc(ren),
		.raddr(raddr[3:0]),
		.rdata (rdata)	
	);
	
endmodule