题解 | #使用8-3优先编码器Ⅰ实现16-4优先编码器#

前15:8 位最优先，输出EO_1 作为后7：0 位的使能端；

若EO_1为1, 则输出0+后8位的输出；若EO_1为0且GS_1 为1，说明前15：8位有输入，则输出为1+前8位的输出。

`timescale 1ns/1ns
module encoder_83(
   input      [7:0]       I   ,
   input                  EI  ,
   
   output wire [2:0]      Y   ,
   output wire            GS  ,
   output wire            EO    
);
assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]);
assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]);
assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]);

assign EO = EI&~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&~I[1]&~I[0];

assign GS = EI&(I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]);
//assign GS = EI&(| I);
         
endmodule

module encoder_164(
   input      [15:0]      A   ,
   input                  EI  ,
   
   output wire [3:0]      L   ,
   output wire            GS  ,
   output wire            EO    
);
   wire [2:0] L_temp1;
   wire [2:0] L_temp2;
   wire GS_1;
   wire GS_2;
   wire EO_1;
   wire EO_2;
   
   encoder_83 c1(A[15:8], EI, L_temp1, GS_1, EO_1);
   encoder_83 c2(A[7:0], EO_1, L_temp2, GS_2,EO_2);

   assign L = EO_1? {GS_1,L_temp2}:
                   ( GS_1? {GS_1,L_temp1}:4'b0000);
   assign GS = GS_1 | GS_2;
   assign EO = EO_2;


endmodule