题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);

	reg [11:0] data_temp;
	reg [1:0] cnt;

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			data_temp <= 12'd0;
		else if(valid_in)
			data_temp <= {data_temp[2:0],data_in};
		else
			data_temp <= data_temp;
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			cnt <= 2'd0;
		else if(valid_in) begin
			if(cnt == 2'd2)
				cnt <= 2'd0;
			else
				cnt <= cnt + 1'b1;
		end
		else
			cnt <= cnt ;
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			valid_out <= 1'b0;
		else if((cnt == 2'd1 || cnt == 2'd2)&& valid_in)
			valid_out <= 1'b1;
		else
			valid_out <= 1'b0;			
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			data_out <= 12'd0;
		else if(cnt == 2'd1 && valid_in)
			data_out <= {data_temp[7:0],data_in[7:4]};
		else if(cnt == 2'd2 && valid_in)
			data_out <= {data_temp[2:0],data_in};
		else
			data_out <= data_out;
	end


endmodule