题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);

	reg [3:0] cnt;
	reg [127:0] data_temp;

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			cnt <= 4'd0;
		else if(valid_in) begin
			if(cnt == 4'd15)
				cnt <= 4'd0;
			else
				cnt <= cnt + 1'b1;
		end
		else
			cnt <= cnt;
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			valid_out <= 1'b0;
		else if((cnt == 4'd5 || cnt == 4'd10 || cnt == 4'd15) && valid_in)
			valid_out <= 1'b1;
		else
			valid_out <= 1'b0;
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			data_temp <= 128'd0;
		else if(valid_in)
			data_temp <= {data_temp[103:0],data_in};
		else
			data_temp <= data_temp;
	end	

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			data_out <= 128'd0;
		else if(cnt == 4'd5 && valid_in)
			data_out <= {data_temp[119:0],data_in[23:16]};
		else if(cnt == 4'd10 && valid_in)
			data_out <= {data_temp[111:0],data_in[23:8]};
		else if(cnt == 4'd15 && valid_in)
			data_out <= {data_temp[103:0],data_in};
		else
			data_out <= data_out;
	end	
	
	
endmodule