题解 | #多功能数据处理器#

module data_select(

    input clk,

    input rst_n,

    input signed[7:0]a,

    input signed[7:0]b,

    input [1:0]select,

    output reg signed [8:0]c

);

always@((487950916)posedge clk or negedge rst_n)begin

    if(!rst_n)

        c   <=  'b0;

    else begin

    case(select)

        2'd0:

            c   <=  a;

        2'd1:

            c   <=  b;

        2'd2:

            c   <=  a   +   b;

        2'd3:

            c   <=  a   -   b;

        default:c=8'b0;

    endcase

    end

end

endmodule