题解 | #序列发生器#
序列发生器
https://www.nowcoder.com/practice/1fe78a981bd640edb35b91d467341061
`timescale 1ns/1ns
module sequence_generator(
input clk,
input rst_n,
output reg data
);
reg [2:0] cnt;
always@(posedge clk or negedge rst_n)
if(!rst_n) cnt<=3'd0;
else if(cnt==3'd5) cnt<=3'd0;
else cnt <= cnt+1'd1;
always@(posedge clk or negedge rst_n)
if(!rst_n) data<=1'b0;
else if(cnt==3'd0) data<=1'b0;
else if(cnt==3'd1) data<=1'b0;
else if(cnt==3'd2) data<=1'b1;
else if(cnt==3'd3) data<=1'b0;
else if(cnt==3'd4) data<=1'b1;
else if(cnt==3'd5) data<=1'b1;
endmodule
基恩士成长空间 440人发布