题解 | #4bit超前进位加法器电路#

`timescale 1ns/1ns

module lca_4(
    input        [3:0]       A_in  ,
    input        [3:0]        B_in  ,
    input                   C_1   ,
     output     wire            CO    ,
    output   wire [3:0]        S
);
wire [4:0]  C;
wire [4:0]  CC;
wire [3:0]  G;
wire [3:0]  P;
assign C[0] = C_1;
genvar i;
    for (i = 0; i < 4; i=i+1) begin
        lca_middle lca_middle_inst (
            .A(A_in[i]), 
            .B(B_in[i]), 
            .C(C[i]), 
            .G(G[i]), 
            .P(P[i]), 
            .S(S[i]), 
            .CC(CC[i+1]));
    assign C[i+1] = CC[i+1];    
    end
assign CO = CC[4];
endmodule

module lca_middle (
    input     A,     
    input     B, 
    input     C, 
    output wire    G,
    output wire    P,
    output wire    S,
    output wire    CC
);
assign G = A&B;
assign P = A^B;
assign CC = G|(P&C);
assign S = P^C;
endmodule
   

#FPGA#