题解 | #四选一多路器#
https://www.nowcoder.com/practice/cba4617e1ef64e9ea52cbb400a0725a3
需要自己写测试用例挺不方便的，而且输出波形要和给出的波形完全一致，有点限制testbench代码书写的灵活性。
`timescale 1ns/1ns
module mux4_1(input [1:0]d1,d2,d3,d0,
input [1:0]sel,
output[1:0]mux_out
);
//*************code***********//
wire [1:0]a,b;
assign a=sel[1]?d0:d2;
assign b=sel[1]?d1:d3;
assign mux_out=sel[0]?a:b;
endmodule
//*************code***********//
//**************testbench***************************//
`timescale 1ns/1ns
module testbench();
// reg clk=0;
// always #5 clk = ~clk; // Create clock with period=10
// A testbench
reg[1:0]d1,d2,d3,d0;
reg[1:0]sel;
wire[1:0]dout;
mux4_1 mux4_1_inst(
.d1(d1),
.d2(d2),
.d3(d3),
.d0(d0),
.sel(sel),
.mux_out(dout)
);
initial begin
d0=2'd3;
d1=2'd0;
d2=2'd1;
d3=2'd2;
sel=2'b00;
#10
sel=2'b01;
#10
sel=2'b10;
#10
$stop;
end
initial begin
$dumpfile("out.vcd");
// This will dump all signal, which may not be useful
//$dumpvars;
// dumping only this module
//$dumpvars(1, testbench);
// dumping only these variable
// the first number (level) is actually useless
$dumpvars(0, testbench);
end
endmodule
module testbench();
// reg clk=0;
// always #5 clk = ~clk; // Create clock with period=10
// A testbench
reg[1:0]d1,d2,d3,d0;
reg[1:0]sel;
wire[1:0]dout;
mux4_1 mux4_1_inst(
.d1(d1),
.d2(d2),
.d3(d3),
.d0(d0),
.sel(sel),
.mux_out(dout)
);
initial begin
d0=2'd3;
d1=2'd0;
d2=2'd1;
d3=2'd2;
sel=2'b00;
#10
sel=2'b01;
#10
sel=2'b10;
#10
$stop;
end
initial begin
$dumpfile("out.vcd");
// This will dump all signal, which may not be useful
//$dumpvars;
// dumping only this module
//$dumpvars(1, testbench);
// dumping only these variable
// the first number (level) is actually useless
$dumpvars(0, testbench);
end
endmodule
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