如何加快系统时钟频率（加法器为例）
假设每个1比特加法环节需要处理的时间是5ns（当然，实际的电路如果这么慢，估计我们敲一个字母计算机都得等上一分钟进行处理）。当四个1bit的加法器级联的环节，处理时间就得20ns，换句话说在这20ns时间范围内我们的输入输出不能有变化，否则将会出现问题。 最终，我们采取模块结构的变化及时序控制的引入来解决这个问题。下面是代码：
module adder_4bits_pipeline(
input[3:0]a,b,
input CLK,
input RST,
output[3:0]sum,
output c
);
reg[2:0]i_a1,i_b1;
reg[1:0]i_a2,i_b2;
reg i_a3,i_b3;
reg D_c0,D_c1,D_c2;
reg o_s0;
reg[1:0]o_s1;
reg[2:0]o_s2;
wire s0,s1,s2,s3;
wire c0,c1,c2,c3;
half_adder H0(.a0(a[0]),.a1(b[0]),.s(s0),.c1(c0));
full_adder F1(.a0(i_a1[0]),.a1(i_b1[0]),.c0(D_c0),s(s1),.c1(c1));
full_adder F2(.a0(i_a2[0]),.a1(i_b2[0]),.c0(D_c1),s(s2,.c1(c2)));
full_adder F3(.a0(i_a3),.a1(i_b3),.c0(D_c2),.s(s3),.c1(c));
assign sum={s3,o_s2};
always@(posedge CLK&nbs***bsp;negedge RST)
begin
if(!RST)
begin
i_a1<=3'b000;
i_b1<=3'b000;
end
else begin
i_a1<=a[3:1];
i_b1<=b[3:1];
end
end
always@(posedge CLK&nbs***bsp;negedge RST)
begin
if(!RST)
begin
i_a2<=2'b00;
i_b2<=2'b00;
end
else begin
i_a2<=i_a1[2:1];
i_b2<=i_b1[2:1];
end
end
always@(posedge CLK&nbs***bsp;negedge RST)
begin
if(!RST)
begin
i_a3<=1'b0;
i_b3<=1'b0;
end
else begin
i_a3<=i_a2[1];
i_a3<=i_b2[1];
end
end
always@(posedge CLK&nbs***bsp;negedge RST)
begin
if(!RST)
begin
D_c0<=1'b0;
D_c1<=1'b0;
D_c2<=1'b0;
end
else begin
D_c0<=c0;
D_c1<=c1;
D_c2<=c2;
end
end
always@(posedge CLK&nbs***bsp;negedge RST)
begin
if(!RST)
begin
o_s0<=1'b0;
o_s1<=2'b00;
o_s2<=3'b000;
end
else begin
o_s0<=s0;
o_s1<={s1,o_s0};
o_s2<={s2,o_s1};
end
end
endmodule 喜欢本文的同学欢迎收藏点赞多多留言，本文原发于【FPGA hdl】
